1. Field of the Invention
The present disclosure relates to structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) to provide a high-Q passive resonator.
2. Description of Related Art
Typically, passive resonators, e.g., inductors and capacitors, are formed in metallization layers, associated with back-end-of-line (BEOL) processes in the making of mixed-signal integrated circuits (ICs), that overlie the bulk silicon (Si) substrates of a Si wafer. After the last front-end-of-line FEOL process, associated with the making of active devices on the bulk Si substrates of the mixed-signal ICs of the Si wafer, there exist isolated active devices such as, transistors, which are not electrically interconnected to form electrical circuits. In the BEOL processes, electrical contacts, wire interconnects, vias and dielectric structures are formed to interconnect the isolated active devices, forming the desired electrical circuits. A passive resonator may also be formed during the BEOL processes above the bulk Si substrate.
Typically, the active devices formed within the FEOL layers are not disposed beneath a passive resonator, because the electric fields generated by the passive resonator adversely affect operation of the active devices. The distance between the passive resonator, formed on top of the BEOL metallization layers to the underlying bulk Si substrate of the mixed-signal IC can range to about 10 μm.
For a passive resonator, the quality factor, Q, is defined in terms of the ratio of the energy stored in the passive resonator to the energy supplied by the generator to keep the signal amplitude constant at the resonant frequency, fr. Typically, an inductor formed on an IC experiences high losses at radio frequencies (RF) and consequently has a low Q value.
One approach to improving Q of a passive resonator formed above a bulk Si substrate of a mixed-signal IC at RF frequencies is to increase the effective “distance” to the underlying bulk Si substrate by increasing the electrical resistance between the passive resonator and the bulk Si substrate. For example, a thick oxide layer of several micrometers thickness when disposed between the passive resonator and the bulk Si substrate improves the Q factor of the passive resonator.
Alternatively, etching the bulk Si substrate underlying an area upon which a passive resonator is to be formed can provide a cavity or air gap of relatively high electrical resistance between the passive resonator and the bulk Si substrate. Anisotropic etchants etch crystalline materials, such as crystalline Si, at very different rates depending on which crystal face or plane is exposed. Referring to FIGS. 1A and 1B, square holes or rectangular holes (not shown), oriented along <110> directions of a (100) crystalline Si wafer (170), are formed in a patterned hard mask 150 on a (100) surface plane of the crystalline Si wafer (170). Anisotropic etching through the square holes or rectangular holes proceeds into the depth of the crystalline Si wafer (170) and spreads laterally until inhibited by {111} etch stop planes of the crystalline silicon.
Thus, in the case of a square hole, a short duration of anisotropic etching forms a cavity of an inverted four-sided trough with trapezoidal sides corresponding to {111} etch stop planes, a base corresponding to the square hole at the (100) surface plane of the crystalline Si wafer (170), and a square surface (dashed line) as shown in FIG. 1B, which corresponds to an etched (100) plane of the crystalline Si wafer (170). A longer duration of anisotropic wet etching through a square hole forms a cavity of an inverted four-sided pyramid, as also shown in FIG. 1B, with triangular sides corresponding to self-limiting {111} etch stop planes and a base corresponding to the square hole at the (100) surface plane of the crystalline Si wafer (170).
Similarly, a short duration of anisotropic wet etching through a rectangular hole, longitudinally-oriented along a [110] direction of the patterned hard mask 150, will form an inverted four-sided trough, longitudinally-oriented along the [110] direction, with trapezoidal sides and end caps corresponding to {111} etch stop planes, a base at the (100) surface plane of the crystalline Si wafer (170) corresponding to the rectangular hole, and a rectangular surface (dashed line), also longitudinally-oriented along the [110] direction, corresponding to an etched (100) plane within the crystalline Si wafer (170). Likewise, a longer duration of anisotropic etching through the rectangular hole, longitudinally-oriented along a [110] direction of the patterned hard mask 150, will form a V-shaped groove, longitudinally-oriented along the [110] direction, with self-limiting triangular end caps and trapezoidal sides corresponding to {111} etch stop planes, and a base at the (100) surface plane of the Si wafer (170) corresponding to the rectangular hole of the patterned hardmask 150.
There remains a need to efficiently form, before the onset of back-end-of-line (BEOL) processes, a dielectric region in a bulk silicon (Si) substrate of a mixed-signal IC, to improve the quality factor, Q, of an overlying passive resonator.